1. Field of the Invention
The present invention relates in general to a semiconductor process, and more particularly, to a method of forming an interlayer dielectric (ILD) layer and a method for preventing formation of etching defects in a contact.
2. Description of the Related Art
As semiconductor device geometries continue to decrease in size to provide more devices per fabricated wafer and faster devices, misalignment between each patterned layer is a serious obstacle. Therefore, many self-aligned processes have been developed in order to prevent misalignment and decrease the interval between devices, thereby increasing the device density.
FIGS. 1a to 1c are cross-sections showing a conventional method of forming a substrate contact (Cs) for a memory device. First, in FIG. 1a, a silicon substrate 100, is provided. The substrate 100 may contain any semiconductor device, such as MOS transistors, and capacitors, used in the memory devices. Here, in order to simplify the diagram, only a flat substrate is depicted. Moreover, the substrate 100 has a peripheral circuit region 10.
Next, a plurality of transistors 106 composed of gate structures 104 and source/drain doping regions 102 is formed on the peripheral circuit region 10. The gate structure 104 is composed of a gate dielectric layer, a gate, a gate capping layer, and a gate spacer.
Thereafter, a borophosphslicate glass (BPSG) layer 108 is formed on the substrate 100 and fills the gap between the gate structures 104 to serve as an interlayer dielectric (ILD) layer. Next, a reflow process is performed on the BPSG layer 108 to make its surface flatter. Next, a photoresist layer 109 is formed on the BPSG layer 108 and lithography is subsequently performed to form an opening 109a therein for defining the substrate contact.
Next, in FIG. 1b, the BPSG layer 108 under the opening 109a is etched using the photoresist layer 109 as a mask to form the substrate contact 110 on the peripheral circuit region 10 to expose the surface of the substrate 100. However, since the thermal stability of the BPSG layer 108 is poor and the BPSG layer 108 easily reacts with moisture, poor etching profiles and etching defects occur in the substrate contact 110 after subsequent lithography and etching, as indicated by the arrow “a” shown in the FIG. 1b. 
Finally, In FIG. 1c, after the photoresist layer 109 is removed, a photoresist pattern layer (not shown) is formed on the BPSG layer 108 to define a trench opening therein. Next, a trench 111 is formed by etching in the BPSG layer 108 near the substrate contact 110. As the integration of integrated circuits increases, the trench 111 is very close to the substrate contact 110. Accordingly, poor etching profiles or defects in the substrate contact 110 result in bridging between a metal plug 112 filled in the substrate contact 110 and a metal layer 114 filled in the trench 111, as the arrow “b” shown in the diagram, the memory device failure.